//Copyright (C)2014-2025 GOWIN Semiconductor Corporation.
//All rights reserved.
//File Title: Timing Constraints file
//GOWIN Version: 1.9.8.06-1 
//Created Time: 2025-03-20 09:28:43
create_clock -name clk_in -period 20 -waveform {0 10} [get_ports {clk_in}] -add
create_generated_clock -name sys_clk -source [get_ports {clk_in}] -master_clock clk_in -multiply_by 2 -duty_cycle 50 -add [get_pins {pll/pllo_inst/CLKOUTA}]
